1. Sequencer
   1. Two independent 8-state sequencers
      1. Dual-sequencer mode
      2. SEQ1
      3. CONV00->CONV07 => RESULT0->RESULT7
      4. SEQ2
      5. CONV08->CONV15 => RESULT8->RESULT15
   2. One 16-state sequencer (SEQ)
      1. Cascaded mode
   3. CONV00->CONV15 => RESULT0->RESULT15
   4. CONVxx can be one of 16 analog inputs
2. Sampling mode
   1. Simultaneous sampling mode
   2. A pair of pins can be sampled and converted
   3. Sequential sampling mode
   4. Only one pin can be sampled and converted
3. Pins selection
   1. CONVxx defines which pins to be selected as a analog input, to be sampled and converted
   2. Via Analog MUX
   3. CONVxx has 4 bits
   4. Sequential mode
      1. All 4 bits define the input pin
      2. 4th bit define which sample-and-hold buffer is selected
      3. 0xxxb for ADCINA0 -> ADCINA7
      4. 1xxxb for ADCINB0 -> ADCINB7
   5. Simultaneous mode
      1. the MSB of CONVxx is discarded
      2. CONVxx = 0110b
         1. ADCINA6 is sampled by S/H-A
         2. ADCINB6 is sampled by S/H-B
      3. Voltage in S/H-A is converted first
         1. followed by S/H-B
      4. ADCRESULT0 for SEQ1, ADCRESULT1 for SEQ2