1. Clock Management Primitives
   1. Relative priority of injection of primitives
      1. Primitive Injection Rate
         1. 1.5Gb/s
            1. one ALIGN or NOTIFY within every 2048 dwords
         2. 3.0Gb/s
            1. two ALIGN or NOTIFY within every 4096 dwords
         3. Higher rate
            1. No requirement for the ALIGNs
         4. Expender
            1. Remove all the ALIGNs and NOTIFYs from an incoming path
            2. Simply insert them at the outgoing Phy as needed
         5. The insertion of primitives for clock management is unrelated to the insertion of other primitives for things like rate matching
2. 8b/10b Encoding and Decoding
   1. Ensure sufficient transitions in the data
      1. Look enough like a clock at the receiver
      2. Used to lock a PLL or other clock recovery scheme
   2. Purpose
      1. Limiting the run length
         1. Run length: length of a contiguous string of 1s or 0s
         2. Each character will have a mix of zeros and ones
         3. No combination of characters would ever be able to create more that 5 ones or zeros in a row
      2. DC balance
         1. Prevent the line from becoming charged up
         2. Also: Disparity balance
         3. More ones than zeros: postive
         4. More zeros than ones: negative
         5. Equal ones and zeros: neutral
         6. When neutral, CRD remains unchanged
      3. Special characters
      4. Minimizing complexity
         1. Split the 8-bit input into 5b/6b and 3b/4b bit sub-blocks
         2. Help with recognition of special characters
   3. 8b/10b Nomenclature
   4. Control Characters and the Comma Pattern
      1. K28.3
         1. STP connection
      2. K28.5
         1. comma pattern
            1. Useful feature for establishing SAS dword synchronization
         2. SAS transaction
      3. K28.6
         1. SATA physical link
         2. SATA_ERROR indicator
         3. Sent by expanders that receive a frame during an STP connection that has an invalid dword or other error
   5. Properties
      1. General
         1. Using disparity forces an equal number of ones and zeros over time
         2. The longest continuous string of either ones or zeros is five
         3. A 10-bit character must have
            1. 5 ones and 5 zeros
            2. 4 ones and 6 zeros
            3. 6 zeros and 4 ones
            4. Not other combination is legal
         4. The 6-bit sub-block cannot contain more than 4 ones or 4 zeros
         5. The 4 bit sub-block cannot contain more than 3 ones or 3 zeros
      2. Bytes, Characters, and Dwords
         1. Byte
            1. 8 bits
         2. Character
            1. The 10-bit result after encoding
         3. Dword
            1. Four bytes
            2. 32 bits
            3. Four characters
            4. 40 bits
         4. Primitive
            1. A dword that begins with a control character and is followed by three data characters that define the meaning of the primitive
            2. Sent out on the wire in this order
            3. Frst is the control character
            4. Followed by three data characters
            5. The endianness of SAS and SATA are different, but for primitives the endianness of both is the same
3. Initialization
   1. Ch. 6
   2. Generation of the Phy reset sequence
   3. Generation of the OOB signaling
   4. Generation of primitives for speed negotiation
4. Implementation Examples
   1. Transmit Block
      1. SSC
         1. Vary the clock over a range of frequencies rather than keeping it fixed as a pure reference clock
         2. Reduce EMI
         3. SSC is optional for SATA
            1. A digital PLL that will support SATA will likely need more feedback bits to cover the wider frequency range than it otherwise would.
         4. Not required for SAS
      2. The frequency of the signals seen on the wire using NRZ encoding must necessarily be less than or equal to half of the transmit frequency
   2. Receive Block
5. Power Management
   1. SAS does not include any power management features
   2. Support of SAS ports acting as SATA host devices
6. Reset
   1. Reasions
      1. Power on
      2. Receiving a Hard Reset OOB pattern
      3. Receiving a management Application Layer request to reset
      4. Losing dword synchronization and not attempting to re-acquire it
      5. Timeout of Receive Odentify timer
      6. For expander phys, after a hot-plug timeout
   2. Hard Reset
      1. If a SAS Phy receives a hard reset it initiates a reset of that port
         1. But not any other ports of the device
         2. SSP Port
            1. Result in a Transport Reset event notification to the SCSI Application Layer
            2. The SCSI device will perform a hard reset
         3. STP port
            1. All the resets are effectively the same
            2. The SATA device will take steps associated with a hardware or power-on reset
         4. Expander ports
            1. Do not forward OOB patterns or hard reset
            2. Do not reset their internal settings, such as routing tables
         5. Wide port
            1. Cause all the phys of that port to reset
   3. Link Reset
      1. SATA
         1. Link reset = Phy reset
      2. SAS
         1. IDENTIFY frame is expected from the attached device after a link reset or hard reset
         2. The Receive Identify Timeout timer is maintained by the SL_IR state machine
            1. Ensure that this frame arrives within 1ms
   4. Phy Reset
      1. 1. OOB sequence
      2. 2. Speed negotiation sequence
7. Phy State Machine
   1. SAS Phy (SP) machine
      1. OOB Sequencing
      2. Speed Negotiaion
         1. SAS
         2. SATA
   2. SAS Phy DWord Synchronization (SP_DWS) machine